1. Field of the Invention
The present invention relates to a method of fabricating a capacitor. More particularly, the present invention relates to a method for fabricating a crown capacitor used in DRAM.
2. Description of the Related Art
In conventional DRAM having a storage capacity less than 1 MB, it is a customary practice to use a two-dimensional capacitor called a planar-type capacitor as the data storage capacitor. One drawback in the planar-type capacitor, however, is that it requires quite a large chip area to implement. Therefore, the planar-type capacitor is not suitable for high-integration DRAM. In DRAM having a storage capacity higher than 4 MB, a three-dimensional capacitor such as a stacked-type capacitor is used as the data storage capacitor. A crown capacitor is a kind of stacked-type capacitor.
FIGS. 1A through 1C are schematic, cross-sectional diagrams used to depict the steps in conventional method for fabricating a crown capacitor.
Referring to FIG. 1A, a substrate 20 having a MOS structure is provided, wherein the MOS structure includes a drain region 24. An inter-layer dielectric layer 26 is formed on the substrate 20. A contact hole 28 is formed in the inter-dielectric layer 26 to expose the drain region 24. A conductive layer 30 is formed on the inter-layer dielectric layer 26 and fills the contact hole 28. The thickness of the conductive layer 30 on the inter-layer dielectric layer 26 is about 6000 .ANG..
Referring to FIG. 1B, an opening 32 is formed in the conductive layer 30 and corresponds to the contact hole 28. The step of forming the opening 32 includes performing an anisotropic etching process to remove a portion of the conductive layer 30 by controlling the duration of etching. The depth of etching is about 4000 to 5000 .ANG..
Referring to FIG. 1C, an anisotropic etching process is performed to remove a portion of the conductive layer 30 by using the inter-layer dielectric layer 26 as a stop layer. Therefore, a bottom electrode 34 is made from the remaining conductive layer 30. A dielectric layer 36 is formed on the bottom electrode 34 and an upper electrode 38 is formed on the dielectric layer 36.
In conventional process for fabricating DRAM whose channel length is below 0.35 .mu.m, two masks are used to form the bottom electrode of the crown capacitor. As the integration of DRAM is increased, the critical dimension of the crown capacitor is reduced. It is hard to meet the demands of the critical dimension of the crown capacitor by using conventional process, because the tolerance of the registration between the two masks is reduced.